In the rapidly evolving landscape of the semiconductor industry, the surge in artificial intelligence (AI) has dramatically transformed market dynamics, bringing new technologies to the forefront and reshaping competitiveness. A significant player in this transformative process is TSMC (Taiwan Semiconductor Manufacturing Company), renowned for its advanced packaging technologies, particularly CoWoS (Chip on Wafer on Substrate), which gained immense popularity in a short span.

The last two years have seen TSMC capitalizing on its CoWoS offering, evidenced by impressive revenue forecasts. In its first-quarter earnings report, TSMC indicated a notable rise in the proportion of advanced packaging in its overall revenue, dispelling market concerns about a decline in CoWoS demand. TSMC's CEO, C.C. Wei, emphasized the company’s commitment to enhancing CoWoS production capacity to meet increasing customer needs, predicting that by 2025, CoWoS could contribute up to 10% of total annual revenue, up from 8% in 2024.

As forecasted, TSMC anticipates a revenue exceeding $90 billion in 2024, which implies that last year alone, CoWoS accounted for over $7 billion in revenue contributions. Such alluring prospects have spurred other packaging companies, particularly ASE (Advanced Semiconductor Engineering) and Amkor, to ramp up investments in their packaging capabilities, eyeing a share of TSMC's lucrative orders amidst capacity constraints.

Recently, ASE made significant strides by announcing plans to establish mass production lines for fan-out panel-level packaging (FOPLP), a technology they have refined over the past decade. FOPLP is gaining traction as a viable alternative to CoWoS, indicating a potential shift in advanced packaging towards a more competitive landscape.

FOPLP's ascent is marked by its innovative approach to integrating semiconductor chips directly within large panels, allowing for unprecedented levels of integration, enhanced electrical performance, and larger package sizes. Compared to traditional packaging methods, FOPLP offers elevated I/O density, improved manufacturing efficiency, and lower production costs, making it increasingly appealing in an industry where cost-effectiveness is paramount.

Understanding FOPLP requires a contextual look at its evolution from Fan-Out Wafer Level Packaging (FOWLP), a technology introduced in 2004 by Infineon and popularized in 2009, which initially found its utility in mobile baseband chips. However, as the market for FOWLP saturated, TSMC found a way to innovate further with the launch of Integrated Fan-Out (InFO) packaging in 2016 for the Apple A10 processor in the iPhone series. This innovation spurred renewed interest and development within the semiconductor community.

FOPLP builds upon the fundamentals of FOWLP, boasting a thicker design with high I/O density, facilitating a greater support for external I/O connections and achieving a slimmer profile at reduced costs. This new technology essentially combines the strengths of fan-out and panel-level packaging methodologies, marking a significant leap towards better cost-efficiency and higher production yields.

Additionally, FOPLP's advantages over wafer-level packaging (WLP) are evident as it employs large panels as substrates. These can be made from various materials, including metals, glass, and polymers, with glass substrates often outperforming others in mechanical and optical properties. Notably, FOPLP also excels in producing larger-sized packages with production flexibility, achieving over 95% area utilization compared to the typical 85% of traditional wafer-level packaging.

The advent of AI has created a demand for larger chip packaging, naturally placing FOPLP at the center of industry attention. According to a report by Yole Intelligence, the FOPLP market was valued at approximately $41 million in 2022 and is projected to grow at a staggering compound annual growth rate (CAGR) of 32.5% over the next five years, potentially surpassing $221 million by 2028. Furthermore, FOPLP’s market share relative to the overall fan-out segment is expected to expand from 2% in 2022 to 8% by 2028, provided that advancements in panel manufacturing and yield improvements are achieved.

Major players in the semiconductor industry are quickly recognizing the potential of FOPLP. ASE, for instance, has been pivotal in pushing this technology forward, with their Chief Operating Officer, Wu Tianyu, noting that the high cost of AI chips necessitates increased packaging density, which elevates risk, thus ensuring strong client support. ASE has invested significantly in the research and development of FOPLP technology over the last decade, moving to larger panel sizes as they approach final testing stages.

Similarly, TSMC is actively championing the FOPLP movement, with CEO C.C. Wei publicly committing to the technology’s advancement. The company is now assembling specialized R&D teams and production lines to expedite its development, with plans for initial outputs expected within three years.

Furthermore, TSMC has been focusing on 300×300 mm panel sizes for its initial deployments. The company's strategy of incrementally increasing the size, considering cost factors and the potential for larger substrates, reflects a carefully calculated approach. They aim to optimize yield rates before scaling to larger dimensions, using a phasing method to ensure that the necessary technology matures alongside the equipment capabilities.

Samsung has also entered the fray, recognizing FOPLP as an essential component for future semiconductor designs. The company's acquisition of PLP business from Samsung Electro-Mechanics in 2019 set the stage for major advancements in this area. Emphasizing the importance of PLP technology during a shareholders' meeting, former Samsung Semiconductor President Kyung Kye-hyun indicated the necessity of adapting to growing chip sizes required for AI applications.

Additionally, Innolux, traditionally a panel manufacturer, is now leveraging its existing production lines to enter the FOPLP market. By taking advantage of its semi-finished equipment, Innolux can significantly reduce costs and increase throughput, achieving efficiencies not possible with conventional models.

Nonetheless, while the prospect for FOPLP looks strong, challenges remain. Research firm TrendForce identifies power management ICs (PMIC), RF ICs, CPUs, and GPUs as prime candidates for FOPLP adoption. PMIC and RF ICs typically utilize chip-first techniques crucial for established packaging operators, while CPU and AI GPU implementations will employ chip-last strategies requiring substantial production experience.

Despite the potential advantages of FOPLP, its current rollout faces roadblocks due to yield rates not yet meeting industry standards and the absence of established specifications. Manufacturers initially ventured into FOPLP as early as 2015; however, transitioning to FOPLP demanded considerable investments in new materials and technologies specifically tailored for panel-level manufacturing.

The growing necessity for AI chips prompted TSMC to ramp up its CoWoS capacity, underscoring a competitive atmosphere where efficiency and adaptability are key. While rumors surfaced regarding Nvidia reducing orders for TSMC’s CoWoS in favor of FOPLP technology, TSMC has since refuted such claims, maintaining that they can meet client demands. However, the shift towards FOPLP lays significant pressure on CoWoS, suggesting an industry in flux and an ever-evolving relationship between packaging technologies in the face of burgeoning AI requirements.